a) Field of the Invention
The present invention relates to a semiconductor device and its manufacture, and more particularly to a dynamic random access memory (DRAM) semiconductor device and its manufacture.
In this specification, a DRAM semiconductor device means a semiconductor device having a DRAM portion, and also includes those having other functional elements.
b) Description of the Related Art
One DRAM cell is generally made of one memory capacitor and one transistor. This transistor is generally an insulating gate (IG) field effect transistor (FET), and typically a metal-oxide-semiconductor (MOS) FET, which is constituted of a pair of source/drain regions, a channel coupling the source/drain regions, and an insulated gate electrode disposed over the channel for controlling the conductivity of the channel.
A memory capacitor is connected to one of the pair of source/drain regions (which is called a source for convenience sake), and a bit line is connected to the other (which is called a drain for convenience sake). A word line is connected to the insulated gate electrode.
For the implementation of a number of memory cells in a limited rectangular area and for the effective read/write of information, it is preferable to dispose bit and word lines orthogonally. Each memory cell is connected to each cross point between bit and word lines.
If one drain region is shared by two transistors and connected to a bit line, an area occupied per one transistor can be reduced. In this case, integrated or merged two transistors are formed in one active region, and the bit line is connected to the central drain region. In order to connect memory capacitors to two sources at opposite end portions of the active region, it is preferable to dispose the active region obliquely relative to the bit lines. Then, word lines become also oblique relative to active regions.
One of the present inventors, Ema, has proposed a DRAM semiconductor device in which the layout of an active region and word lines of each memory cell is devised to stabilize the threshold values of transistors even under misalignment of patterning (Japanese Patent Laid-open Publication HEI-2-192162 and U.S. Pat. No. 5,014.013 issued on May 7, 1991, which are incorporated herein by reference).
FIG. 5 shows the layout of memory cells proposed by Ema. A plurality of bit lines BL extend straight and in parallel in the horizontal direction in FIG. 5. Bit lines disposed straight can minimize their resistance values. Each active region AR is disposed obliquely (about 30 degrees) relative to bit lines BL.
In an area where the active region AR crosses the bit line BL, a contact portion BL' of the bit line is formed which is wider than the other portion of the bit line. A bit line contact hole BH is formed through an interlayer insulating film disposed between the active region AR and bit line BL. A capacitor contact hole SH is disposed generally at the center of an area surrounded by two adjacent bit lines BL and two adjacent word lines WL. Namely, the distance from the capacitor hole to nearest bit/word lines is maximized.
A storage electrode SE of the capacitor is disposed around the capacitor contact hole SE in an area between upper and lower bit lines BL, the electrode covering the adjacent word line.
In the area between the bit line contact hole BH and capacitor contact hole SH, the active region AR extends straight at a constant width. The active region AR includes a region AR' to reserve an area under the capacitor contact hole, this region AR' having a shape symmetrically folded relative to a virtual vertical line passing through the center of the capacitor contact hole SH.
A word line WL extends as a whole in a vertical direction of FIG. 5. However, this word line is curved around the center of the contact hole of the bit line BL In an area crossing the bit line, connected to the corresponding active region AR. The word line WL can therefore be disposed generally at a right angle relative to the active region AR. With this layout, even if there is any position alignment error between the word line WL and active region AR, the threshold value of each transistor can be maintained constant.